Evolving standards for wireless data communication increase demands with respect to error vector magnitude (EVM) and spectral purity. This may lead to stricter requirements on local oscillator (LO) integrated phase noise and spurs.
Fractional-N digital phase lock loops (DPLLs) are increasingly being used for local oscillator (LO) generation. This may be attributable to:
lower area and power consumption relative to analog fractional-N PLLs;
ease of porting and scalability amongst process generations;
process, voltage, and temperature (PVT) insensitive loop dynamics; and/or
programmability/re-configurability of loop performance.
A DPLL may include a time-to-digital converter (TDC) to measure and digitally encode an instantaneous phase of a PLL clock relative to a reference clock. Non-linearity and/or insufficient resolution of a TDC may result in spurs and impact spectral purity. Conventional techniques to reduce non-linearity and/or increase resolution may increase area and/or power consumption.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.